1. Field of the Invention
The invention relates to a protection device, and more particularly to an electrostatic discharge (ESD) protection device receiving high operation voltage.
2. Description of the Related Art
As the semiconductor manufacturing process develops, ESD protection has become one of the most critical reliability issues for integrated circuits (IC). In particular, as semiconductor process advances into the deep sub-micron stage, scaled-down devices and thinner gate oxides are more vulnerable to ESD stress. Generally, a conventional method is to integrate an ESD protection device in ICs.
Different ESD protection devices have different holding voltages (Vh) and different trigger voltages (Vtl). Generally, the holding voltage (Vh) is higher than an operation voltage (VDD) to avoid latch-up problems caused by surges in voltage. During a low voltage operation, the holding voltage is typically higher than the operation voltage. Thus, standard ESD protection devices can be utilized.
However, during a high voltage operation, the holding voltage is typically less than the operation voltage (VDD). Thus, a latch-up problem may occur. To avoid the latch-up problem, a conventional method used is to increase the holding voltage. However, the trigger voltage of the ESD protection device is also increased when the holding voltage is increased. Thus, reducing the efficiency of the ESD protection device.
To increase the efficiency of the ESD protection device, another conventional method is to use a gate-grounded NMOS (GGNMOS) or a silicon controlled rectifier (SCR) as an ESD protection device. FIG. 1 is a schematic diagram of a conventional GGNMOS. FIG. 2 is a schematic diagram of a conventional N-type SCR.
Although the conventional GGNMOS or the NSCR can increase the efficiency of the ESD protection device, the holding voltage of the ESD protection device cannot be increased and the trigger voltage of the ESD protection device cannot be reduced. FIG. 3A is a schematic diagram of a conventional series GGNMOS. FIG. 3B is an equivalent circuit of the conventional series GGNMOS shown in FIG. 3A. Since the GGNMOSs are connected in series, the holding voltage of the ESD protection device can be increased.
However, the trigger voltage of the ESD protection device is also increased when the holding voltage is increased. Thus, a resistor R and a capacitor C are utilized to reduce the trigger voltage of the ESD protection device. Although the structure of the ESD protection device shown in FIG. 3A, allows the holding voltage of the ESD protection device to be increased and the trigger voltage of the ESD protection device to be reduced, a leakage current problem occurs.
FIG. 3C is a characteristic diagram of the series GGNMOS shown in FIG. 3A. The curve 31 represents a relationship between the voltage and the current of the series GGNMOS shown in FIG. 3A. The curve 32 represents a relationship between the voltage and the leakage current of the series GGNMOS shown in FIG. 3A.
As shown in the curve 32, leakage current of a series GGNMOS is suddenly increased when snapback breakdown occurs.